Scalable UVM Frameworks Augmented With ML For Multi-Protocol Storage Soc Verification

Abstract

In the modern semiconductor industry, storage system-on-chip designs must support multiple high-speed protocols, including PCIe, NVMe, SATA, and NAND flash interfaces with increasingly complex design topologies. Customary Universal Verification Methodology (UVM) frameworks continue to face important limitations, as they do not consider the exponential growth of design state spaces, protocol interplays, and system-level integration scenarios in modern storage controller designs. Other suggested extensions to customary verification methodologies include smart test generation from a reinforcement learning agent, automated coverage optimization and clustering from machine learning techniques and predictive analytics, and discovery of cross-protocol interactions through graph neural networks and sequence-to-sequence modeled topologies. Coupled with existing UVM base classes, a machine learning inference engine (or engines) can be selectively instantiated, preserving the modularity and reusability intrinsic to the UVM methodology while introducing artificial intelligence to the production verification flow. While practical benefits will be realized beyond pilot programs by addressing compute overhead management, training data collection and curation, interpretability and machine learning integration within legacy electronic design automation (EDA) tool frameworks, machine learning methods mapped to Universal Verification Methodology (UVM) frameworks represent state-of-the-art incremental steps in the progression of semiconductor verification in improved coverage ratio, bug discovery efficiency and resource efficiency backward compatible to legacy flows to help verification teams combat the verification complexity crisis of next-generation storage system-on-chip design.