An Intelligent Retiming-Based Optimization Framework for High-Performance FIR Digital Filter Architectures Using Improved Hippopotamus Optimization Algorithm

Abstract

Finite Impulse Response (FIR) digital filters are essential components in digital signal processing systems; however, high-order FIR filter implementation faces challenges related to hardware complexity, register utilization, and critical path delay. Retiming techniques provide an effective solution for improving the speed and resource efficiency of VLSI-based FIR architectures by optimizing the placement of memory elements. This research presents an intelligent retiming-based optimization framework using an Improved Hippopotamus Optimization (IHO) algorithm for enhancing FIR filter performance. The proposed approach combines retiming transformation with metaheuristic optimization to achieve efficient register distribution and improved timing characteristics. The performance of the optimized FIR architectures is evaluated using multiple parameters, including register count, clock period, operating frequency, and execution time. Comparative analysis with Hippopotamus Optimization (HO), Schooling Aquatic Optimization (SchoA), and Moth Flame Optimization (MFO) demonstrates the effectiveness of the proposed method. The optimized FIR-TDF10 architecture achieves an improvement in operating frequency from 108.24 MHz to 175.91 MHz, along with reduced register utilization and enhanced computational efficiency. The results confirm that the proposed IHO-based retiming framework provides an effective approach for designing high-speed and area-efficient FIR digital filters for advanced VLSI applications.