Artificial Intelligence for VLSI Reliability: A Comprehensive Review of Machine Learning, Deep Learning, and Explainable AI for Fault Prediction and Diagnosis

Abstract

The current trend of VLSI technologies focus on increasing chip complexity and efficiency by minimizing the size of the transistors which led to complexity in predicting and preventing faults in IC Fabrication.  Traditional methods of fault detection are slow that cannot cope up with advanced Complex chip designs. Due to the advancements of the driving technologies machine learning (ML) algorithms have exponentially increased to foretell faults in VLSI circuits more precisely and effectively. This study explores different machine learning (ML) algorithms, categorizing them into supervised, unsupervised, and deep learning, and also discusses hybrid models to identify some common faults in VLSI circuits including stuck-at faults, bridging faults, open circuits and delay faults. Also the work focuses on the ways the data are gathered, that are significant in the process of training models and their evaluation performance. The paper discusses the on-going challenges in fault prediction and highlights how emerging techniques such as explainable AI can help address these complexities more effectively. This paper is a review-based study that aims to review and compare previous research on VLSI predicting faults and diagnosis using ML, DL and XAI techniques, without any independent simulation or experimental validation.

A total of 23 research papers published from 2020 to 2025 underwent through evaluation to gauge the utility of machine learning (ML), Deep Learning (DL) and hybrid models for VLSI fault prediction. The investigations are appraised using performance metrics, accuracy, precision, recall and F1 score. The review dissects diverse fault prediction paradigms, pre-processing techniques, feature extraction approach and learning infrastructure to diagnose faults in VLSI circuits. Future fault diagnosis systems using XAI, hybrid models are also discussed for future research needs in VLSI testing.