Fault-Tolerant Arithmetic Logic Unit Design Using Quantum Dot Cellular Automata for Reliable Nanoelectronics Systems

Abstract

Quantum-Dot Cellular Automata (QCA) offer a promising alternative to conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology for compact and energy-efficient nanoelectronics circuit design. However, previous QCA-based Arithmetic Logic Unit (ALU) designs have mainly emphasized optimization, reversible computation, or individual fault-tolerant circuits, with limitations in simultaneously achieving compactness, low delay, and reliable operation under multiple fault conditions. This study aimed to develop a fault-tolerant QCA-based ALU addressing these limitations. The proposed methodology involved designing a majority gate, full adder, 4:1 multiplexer, logic unit, and arithmetic unit, followed by their integration into a complete ALU. Functional verification, fault injection analysis, performance evaluation, and statistical validation were subsequently performed using QCADesigner. The proposed ALU achieved 206 cells, an occupied area of 0.455 μm², a 0.5 clock-cycle delay, and 0.0730 eV energy dissipation, with an overall 94.25% fault reliability. The comparative analysis demonstrated improved compactness and competitive delay relative to the considered existing designs. The study concludes that the proposed architecture provides a reliable and compact solution for QCA-based nanoelectronics. Overall, the results demonstrate the feasibility of fault-tolerant QCA-based ALU design for emerging reliable and scalable nanoelectronic systems, supporting their potential integration into future high-density computational architectures.