Machine Learning-Based Static Timing Analysis for Advanced Semiconductor Design: Approaches, Challenges, and Solutions

Abstract

This article discusses the growing performance and energy efficiency challenges with STA needed for sub-10nm technology nodes and the associated resource limitations of conventional EDA tools in achieving timing closure. With machine learning techniques, important cell-arc and wire delay estimation speedups are achieved through the training of predictive machine learning models over design data with representative characteristics. This enables wire delay estimation with a high degree of accuracy and within acceptable limits. The two main challenges in wire delay estimation methods are global routing versus detailed routing miscorrelation and parasitic parameter estimation. Process variation modeling of devices must include SPICE-trained cell delay models in addition to variations in parameters such as crosstalk, temperature, and voltage variations, and distance-based variation, and may employ a combined neural network. In addition, Electromigration (EM) induced self-heating, and IR drop hotspots can be predicted by ML models trained on proper design features. Depending on the requirements, such as speed, accuracy, and availability of hardware resources, the regression may be performed using linear regression, random forest ensemble regression, or deep neural networks. Employing these regression models has resulted in run-times on ECO phases exceeding 1000 times faster march to tape-out and signoff.